Alif Semiconductor /AE722F80F55D5AS_CM55_HE_View /ETH /ETH_DMA_CH0_STATUS

Transmit Interrupt This bit indicates that the packet transmission is complete. When transmission is complete, Bit 31 of TDES3 is reset in the last descriptor, and the specific packet status information is updated in the descriptor. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.

0 (Val_0x0): Transmit interrupt status not detected

1 (Val_0x1): Transmit interrupt status detected

Transmit Process Stopped This bit is set when the transmission is stopped. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.

0 (Val_0x0): Transmit process stopped status not detected

1 (Val_0x1): Transmit process stopped status detected

Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list, and the DMA cannot acquire it. Transmission is suspended. the ETH_DMA_DEBUG_STATUS0[TPS0] field explains the Transmit Process state transitions. To resume processing the Transmit descriptors, the application should do the following:

1. Change the ownership of the descriptor by setting Bit 31 of TDES3.
2. Issue a Transmit Poll Demand command. For ring mode, the application should advance the Transmit Descriptor Tail Pointer register of a channel. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.

0 (Val_0x0): Transmit buffer unavailable status not detected

1 (Val_0x1): Transmit buffer unavailable status detected

Receive Interrupt This bit indicates that the packet reception is complete. When packet reception is complete, Bit 31 of RDES3 is reset in the last descriptor, and the specific packet status information is updated in the descriptor. The reception remains in the Running state. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.

0 (Val_0x0): Receive interrupt status not detected

1 (Val_0x1): Receive interrupt status detected

Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list, and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors, the application should change the ownership of the descriptor and issue a Receive Poll Demand command. If this command is not issued, the Rx process resumes when the next recognized incoming packet is received. In ring mode, the application should advance the Receive Descriptor Tail Pointer register of a channel. This bit is set only when the DMA owns the previous Rx descriptor. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.

0 (Val_0x0): Receive buffer unavailable status not detected

1 (Val_0x1): Receive buffer unavailable status detected

Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.

0 (Val_0x0): Receive process stopped status not detected

1 (Val_0x1): Receive process stopped status detected

Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received.

0 (Val_0x0): Receive watchdog timeout status not detected

1 (Val_0x1): Receive watchdog timeout status detected

Early Transmit Interrupt This bit when set indicates that the Tx DMA has completed the transfer of packet data to the MTL TXFIFO memory. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.

0 (Val_0x0): Early transmit interrupt status not detected

1 (Val_0x1): Early transmit interrupt status detected

Early Receive Interrupt This bit when set indicates that the Rx DMA has completed the transfer of packet data to the memory. The setting of RI bit automatically clears this bit. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.

0 (Val_0x0): Early receive interrupt status not detected

1 (Val_0x1): Early receive interrupt status detected

Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). When this bit is set, the corresponding DMA channel engine disables all bus accesses. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.

0 (Val_0x0): Fatal bus error status not detected

1 (Val_0x1): Fatal bus error status detected

Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error, which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one’s descriptor in Tx case and on Rx side it indicates DMA has read a descriptor with either of the buffer address as ones which is considered to be invalid. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.

0 (Val_0x0): Context descriptor error status not detected

1 (Val_0x1): Context descriptor error status detected

Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the ETH_DMA_CH0_INTERRUPT_ENABLE register: Bit 1: Transmit Process Stopped Bit 7: Receive Buffer Unavailable Bit 8: Receive Process Stopped Bit 10: Early Transmit Interrupt Bit 12: Fatal Bus Error Bit 13: Context Descriptor Error This is a sticky bit. The user must clear this bit (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.

0 (Val_0x0): Abnormal interrupt summary status not detected

1 (Val_0x1): Abnormal interrupt summary status detected

Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the ETH_DMA_CH0_INTERRUPT_ENABLE register: Bit 0: Transmit Interrupt Bit 2: Transmit Buffer Unavailable Bit 6: Receive Interrupt Bit 11: Early Receive Interrupt This is a sticky bit. The user must clear this bit (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set is cleared. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect.

0 (Val_0x0): Normal interrupt summary status not detected

1 (Val_0x1): Normal interrupt summary status detected

Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example, error response on the AXI interface. Bit 18 0x0: No error during data transfer by Tx DMA 0x1: Error during data transfer by Tx DMA Bit 17 0x0: Error during data buffer access 0x1: Error during descriptor access Bit 16 0x0: Error during write transfer 0x1: Error during read transfer

Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example, error response on the AXI interface. Bit 21 0x0: No error during data transfer by Rx DMA 0x1: Error during data transfer by Rx DMA Bit 20 0x0: Error during data buffer access 0x1: Error during descriptor access Bit 19 0x0: Error during write transfer 0x1: Error during read transfer